# 12.288MHz = 256*fs=256*48KHz

w 30 00 00
w 30 01 01  # SW reset
w 30 00 01	# select page1
w 30 01 00	# enable weak connection<AVDD weak connect to DVDD>
w 30 02 21	# ALDO pwr up and output 1.77V, DLDO output 1.72V, no over current detect in ALDO and DLDO
w 30 7B 01	# set reference power-up time: 40ms when analog block pwr up
w 30 00 00	# setting for I2S and clock settings
w 30 06 20  # J=4.
w 30 05 12  #  pll pwr down, P=1, R=2.
w 30 04 07  # PLL_CLKIN = MCLK; CODEC_CLKIN = PLL_CLK.
w 30 07 00  #  D LSB = 0.00
w 30 08 00  #  D MSB = 0.00
w 30 05 92  # PLL power up p=1,R=2
w 30 0B 82  # NDAC up, NDAC=2.
w 30 0C 88  # MDAC up, MDAC=8.          
w 30 12 82  # NADC up, NADC=2.
w 30 13 88  # MADC up, MADC=8.
w 30 00 01	# Set up downlink path connection
w 30 0A 3B  # Both Line and HP Powered by LDOIN_3V3, CM setting is set to 1.65V
w 30 0C 08	# Connect LDAC to HPL
w 30 0D 08 	# Connect RDAC to HPR
w 30 0E 08	# Connect LDAC to LOL
w 30 0F 08	# Connect RDAC to LOR
w 30 10 00	#  HPL driver is not mute, HPL gain =0dB                         
w 30 11 00  #  HPR driver is not mute, HPR gain =0dB                        
w 30 12 00	#  LOL driver is not mute, LOL gain =0dB                       
w 30 13 00	#  LOR driver is not mute, LOR gain =0dB                         
w 30 00 00	# unmute DA and AD                   
w 30 40 00  #  left right DAC is not mute, Right and left DAC has independent volume control                        
w 30 52 00	#  left right ADC are not mute, right and left ADC gain =0dB                        
w 30 1B 00	#  Audio interface = I2S, data word length = 16bit, Bclk & WCLK is input to device
w 30 1D 00  #  Audio interface -- no loopback, default bit clock polarity, primary BCLK and WCLK buffers pwr up, BDIV_CLKIN = DAC_CLK
w 30 1E 00	#  pwr down BCLK N divider